1. Field of the Invention
The present invention relates generally to a static memory having a self-timing circuit for generating timing control signals such as starting signals for a sense amplifier, and more particularly to a static memory which prevents occurrence of a malfunction caused by a leak current of a cell transistor.
2. Description of the Related Art
A static memory has memory cells each of which is a pair of cross-connected inverters. The pair of inverters of the memory cells is connected to a bit line pair via a pair of transfer transistors, and the transfer transistors are conductive according to a driving of a word line, and the inverter pair of the memory cell is connected to the bit line pair, and the inverter pair drives the bit line pair. A voltage difference of the driven bit line pair is detected and amplified by a sense amplifier. Accordingly, a start timing of the sense amplifier is designed so as to come after the voltages of the bit line pair are sufficiently opened.
In a clock synchronous static memory, a timing control signal for starting the sense amplifier is generated after a certain delay time from a supply of a clock, and further in a clock asynchronous static memory, the timing control signal for starting the sense amplifier is generated after a certain delay time from a change of an address.
Preferably, the sense amplifier starting signal is generated at the shortest timing after a predetermined voltage difference is generated between the bit line pair, thereby reducing an access time. However, the bit line drive capability of the memory cells depends on a characteristic of cell transistors, and the characteristic of the cell transistors various due to variances of a manufacturing process. In this manner, as a time for which a predetermined voltage difference is generated between the bit line pair depends on the variances of the process, a sufficient timing margin is provided to generate the sense amplifier starting signal. Even if the timing when the predetermined voltage difference is generated between a bit line pair delays due to the variances towards lower drive capability in the cell transistors, this timing margin allows to prevent a detection of erroneous data by early starting the sense amplifier.
The timing margin of the sense amplifier starting signal prolongs the access time of the memory, and impairs the high-speed performance as the characteristic of the static memory. As a method for solving this problem, a dummy circuit comprising a word line, a memory cell and a bit line is provided, and the sense amplifier starting signal is generated by utilizing a self-timing circuit including this dummy circuit.
FIG. 1 is a configuration diagram of a static memory having a conventional self-timing circuit. In this example, an address Add and a control signal Cont are input in synchronism with a clock CK, and a timing control circuit and a decoder circuit 10 generate timing control signals xcfx86WA, xcfx86SE, a word line selecting signal RS and a column selecting signal CS. A word line driver 12 drives a word line WL according to the word line selecting signal RS generated by the decoder circuit to select a memory cell MC within a memory cell array MCA. The selected memory cell MC drives a bit line pair BL, XBL, and a voltage of the bit line pair selected by a column switch 14 is amplified by a sense amplifier 18. A data output Dout is output from an output circuit 22. The above is a readout operation. In a write operation, a data input Din is input into an input circuit 20, and the selected memory cell MC is driven by a write amplifier 16, so that data is written.
In the readout operation, a timing of a starting signal xcfx86SA for starting the sense amplifier 18 is controlled by the self-timing circuit comprising a dummy word line DWL, a self-timing dummy memory cell SDMC, a dummy bit line pair DBL, XDBL and a dummy timing control circuit 24.
The dummy word line DWL having a plurality of load dummy cells LDMC, a self-timing dummy memory cell SDMC and a dummy bit line pair DBL, XDBL having the plurality of load dummy cells LDMC are provided with a configuration equivalent to a normal memory cell array.
FIG. 2 is a timing chart diagram of a readout operation of FIG. 1. In the readout operation, in a status that the bit line pair BL, XBL is pre-charged at H level, the word line driver 12 drives the selected word line WL as well as the dummy word line DWL. A self-timing dummy memory cell SDMC is selected in response thereto to drive the dummy bit line pair DBL, XDBL. Specifically, a potential level of one dummy bit line is decreased from the pre-charge level. A change xcex94V of the voltage of this dummy bit line pair is detected, and a dummy timing control circuit 24 generates a self-timing signal xcfx86SLF. The timing control circuit 10 generates the sense amplifier starting signal xcfx86SA in response to this self-timing signal xcfx86SLF.
On the other hand, the memory cell MC selected by driving of the selected word line WL drives the bit line pair BL, XBL. In response to the sense amplifier starting signal xcfx86SA, the sense amplifier 18 detects the voltage difference xcex94V of the selected bit line pair to drive one of the bit line pair down to sufficiently low level.
According to the dummy circuit, drive capability of the memory cell MC in the memory array varies due to process variances, but drive capability of the dummy memory cell SDMC similarly varies. Accordingly, a timing when a voltage difference to be detected by the sense amplifier occurs in the bit line pair BL, XBL driven by the memory cell MC and a timing when a predetermined voltage difference occurs in the dummy bit line pair DBL, XDBL driven by the dummy memory cell SDMC vary in the same direction according to the process variances. As a result, the sense amplifier starting signal xcfx86SA is always generated at an optimal timing.
Incidentally, in FIG. 2, a reduction in a voltage of the dummy bit line pair DBL, XDBL is faster than a normal bit line pair BL, XBL. This is because the self-timing dummy memory cell SDMC is configured by connecting a plurality of memory cells in parallel, so as to have a higher drive capability than a piece of memory cell. Thus, a voltage change of the dummy line pair is made faster than the normal bit line pair, thereby making it possible to generate a self-timing signal xcfx86SLF at an early timing.
FIG. 3 is a detailed circuit diagram of the dummy bit line pair and the dummy memory cell connected thereto in the prior art. The self-timing dummy memory cell SDMC has a latch circuit in which a pair of inverters INV1, 2 are cross-connected to each other, and transfer transistors N5, N6 for connecting then to the bit line pair DBL, XDBL. A plurality of the dummy memory cells SDMC (not shown) are connected in parallel to the dummy word line DWL. Furthermore, load dummy memory cells LDMC1, 2 also have the pair of inverters INV1, 2 and the transfer transistors N5, N6, similarly. However, word lines LDWL1, 2 connected thereto are fixed to a ground potential Vss. Accordingly, the load dummy memory cells are provided only for giving the same parasitic capacitance as the normal memory cell to the dummy bit line pair DBL, XDBL, and does not drive the dummy bit line pair.
As the plurality of self-timing dummy memory cells SDMC are provided in parallel, one of a pair of nodes n1, n2 of an inverter pair is fixed to a potential at H level or L level so that a conflict does not generate in operations of driving the dummy bit line pair when the dummy word line DWL is driven. In an example of FIG. 3, the node n1 is connected to a power supply Vcc. As a result, according to the driving of the dummy word line DWL, a right-side dummy bit line XDBL among the dummy bit line pair which has been pre-charged in advance is driven to L level side by the inverter INV1 via the transfer transistor N6. In other words, the dummy bit line XDBL is driven according to an illustrated discharge current I0. Behavior of this dummy bit line is fixed.
However, the load dummy memory cells LDMC1, 2 not relating to the driving of the dummy bit line are configured in the same manner as the normal memory cell, and the pair of nodes n1, n2 are set to H or L level when the power supply on. A status of the load dummy memory cells LDMC1, 2 is unspecified differing from the self-timing dummy memory cell SDMC.
The self-timing dummy memory cells SDMC and the load dummy memory cells LDMC are provided in the same number as the memory cells of the memory cell array. The self-timing dummy memory cells SDMC are configured only by connecting at most approximately 4 pieces to 8 pieces of cell in parallel, and the remaining many cells are the load dummy memory cells.
Now, assuming that all the load dummy memory cells LDMC come to a status that the node n1 is in H level and the node n2 is in L level. Although the transfer transistors N6 are in a nonconductive state, the transistors N6 flow a certain leak current. In particular, according to a trend of a low threshold voltage of a semiconductor memory in late years, the leak current of transistors increases. As a result, a leak current I1 flows from the right-side dummy bit line XDBL of the dummy bit line pair. The leak current per se is an extremely small current, but as the number of load dummy memory cells is many, when totalizing them, the total becomes a relatively large current.
For this reason, as shown in the timing chart diagram of FIG. 4, the right-side dummy bit line XDBL is also driven from the pre-charge level to the L level by the leak current I1 in addition to the drive current I0 of the self-timing dummy memory cells SDMC. The drive speed is faster than as shown in FIG. 2. For this reason, a timing when a predetermined potential difference xcex94V is generated in the dummy bit line pair is made faster, and a rising timing of the self-timing signal xcfx86SLF is made faster, and finally a timing of the sense amplifier starting signal xcfx86SA is also made faster. The timing shown by a broken line of FIG. 4 is an optimal timing of the sense amplifier starting signal xcfx86SA, but an early timing is generated as shown by a solid line. As a result, when the sense amplifier 18 is activated while a sufficient potential difference does not generate in the bit line pair BL, XBL, there is a possibility that the erroneous readout data are output from the sense amplifier. Namely, a malfunction occurs due to the leak current.
It is therefore an object of the present invention to provide a static memory which prevents occurrence of the malfunction.
Another object of the present invention is to provide a static memory which prevents a malfunction from occurring due to a fact that a self-timing circuit configured by dummy cells makes a timing of a sense amplifier starting signal too fast.
In order to achieve the above objects, according to an aspect of the present invention there is provided a static memory including a memory cell array having a plurality of word lines, a plurality of bit line pairs, and memory cells, disposed at cross sections thereof, each having a pair of nodes which hold opposite levels; the static memory comprising a dummy circuit disposed along the memory cell array, having a dummy word line, a dummy bit line pair, a self-timing dummy memory cell which are connected to the dummy word line and dummy bit line pair and have a pair of nodes holding opposite levels, and a plurality of load dummy memory cells connected to the dummy bit line pair; and a timing control circuit for detecting a voltage change of the dummy bit line pair to generate a timing control signal, i. g. a start signal to a sense amplifier for amplifying the bit line pair. The pair of nodes of the self-timing dummy memory cell are fixed to a first status, and the pair of nodes of the load dummy memory cell are fixed to a second status opposite to the first status.
According to the present invention, when the dummy bit line pair is driven by the self-timing dummy memory cell in which the pair of nodes are fixed to the first status, as the load dummy memory cell is fixed to a different status from the self-timing dummy memory cell, this prevents from making the driving of the dummy bit line pair excessively early due to the leak current of the load dummy memory cell unlike the prior art. As a result, it is possible to generate the sense amplifier starting signal after a generation of the sufficient voltage difference in the bit line pair. Moreover, it is possible to generate the sense amplifier starting signal at the optical timing corresponding to the characteristic variances of the cell transistors due to a manufacturing process or the like.
In the preferred embodiment of the present invention, one of the pair of nodes of the self-timing dummy memory cell is fixed to the first voltage level. On the other hand, one of the pair of nodes of the load dummy memory cell is fixed to the second voltage level opposite to the first voltage level, or another node is fixed to the first voltage level. The first and second voltage levels are a power supply level or a ground level, for example.
In the preferred embodiment of the present invention, all the plurality of load dummy memory cells are fixed to the opposite status to the self-timing dummy memory cell. As a result, all the load dummy memory cells always maintain the opposite status to the self-timing dummy memory cell, and the leak current prevents the driving of the dummy bit line pair from being made faster, and can prevent the malfunction.
In another preferred embodiment, at least some of the plurality of load dummy memory cells may be fixed to the opposite status to the self-timing dummy memory cell. As a result, it is prevented that all the load dummy memory cells hold the same status as the self-timing dummy memory cell, and the malfunction occurs due to a fact that the driving of the dummy bit line pair is excessively made faster by the leak current. Namely, it is possible to prevent a worst status.
Furthermore, in a further embodiment, some of the plurality of load dummy memory cells are fixed to the opposite status to the self-timing dummy memory cell, and the residue are fixed to the same status. By doing so, as it is possible to always set the behavior of the leak current due to the load dummy memory cell in the same status, this can prevent such a fact that a driving operation of the dummy bit line pair fluctuates by an indefinite status of the load dummy memory cell to contain a possibility of causing the malfunction. Moreover, it is possible to prevent a worst status.
According to a second aspect of the present invention, the load dummy memory cells are initially set to the opposite status to the status of the self-timing dummy memory cell. Namely, instead of fixing one node or another node of the load dummy memory cells to a predetermined voltage level to fix them to the opposite status to the self-timing dummy memory cell, according to the second aspect, the load dummy memory cell is set to the opposite status to the status of the self-timing dummy memory cell and holds such status when the memory is initially set. For this reason, a reset operation of the load dummy memory cell is carried out when performing the initial setting. As the load dummy memory cell is not driven by the word line, when the status has once been set, the status is maintained until the power supply is turned off.